1. Technical Field
The disclosure relates in general to a replacement gate process and device manufactured using the same, and more particularly to the replacement gate process capable of controlling a gate height of a device and the device manufactured using the same.
2. Description of the Related Art
Size of semiconductor device has been decreased for these years. Reduction of feature size, improvements of the rate, the efficiency, the density and the cost per integrated circuit unit are the important goals in the semiconductor technology. The electrical properties (such as junction leakage) of the device have to be maintained even improved with the decrease of the size, to meet the requirements of the commercial products in applications. The high k-metal gate (HKMG) technique has been developed, and the logic device with the HKMG structure offers quite a few advantages in terms of power reduction and performance improvements, particularly in the datapath and other high-speed areas.
The high k-metal gate (HKMG) process could be divided into two common process of gate-first and gate-last. Taken the gate-last HKMG process (also known as the replacement gate process) for example, a dummy gate is formed by material such as polysilicon or amorphous silicon, and the dummy gate is then removed and replaced by a metal gate. In another aspect, a high-K dielectric film is one of the important features in the semiconductor manufacturing of memory applications, which increases the capacity of the memory. In the HKMG process, the high-K dielectric film could be formed before manufacturing the dummy gate, which is a so-called high K first-HKMG process. The high-K dielectric film could be formed after the manufacture and removal of the dummy gate, which is a so-called high K last-HKMG process. No matter which process is adopted to pattern a HKMG stack, the gate height of the gate and topography of the stack should be precisely controlled for obtaining a semiconductor device with excellent electrical performance.
FIG. 1A˜FIG. 1D illustrate a conventional high K-metal gate process. As shown in FIG. 1A, a substrate 10 with a dummy gate 12 is provided, and the dummy gate 12 includes a polysilicon layer 121 and a hard mask layer 122. Spacers 14 are formed on the sidewalls of the dummy gate 12, wherein the spacers 14 could be one layer, or multi-layer such as the first spacer 141 and the second spacer 142 depicted in FIG. 1A. Also, a contact etch stop layer 16 is formed on the substrate and covers the spacers 14, and an interlayer dielectric (ILD) layer 17 formed on the contact etch stop layer 16. An epitaxy layer 101 could be selectively grown on the substrate 10. As shown in FIG. 1B, the interlayer dielectric layer 17 is planarized by chemical mechanical polishing (CMP), and the upper surface of the contact etch stop layer 16 is exposed. As shown in FIG. 1C, the structure is then subjected to dry etching to remove parts of the interlayer dielectric layer 17, the contact etch stop layer 16 and the dummy gate 12, wherein the hard mask layer 122 is completely removed and the polysilicon layer 121 is partially removed. As shown in FIG. 1D, the remained polysilicon layer 121′ is removed by wet etching to form a trench 18. A metal layer is filled in the trench 18, followed by planarization to form a metal gate (not depicted in Figures).
In the current HKMG process, the spacers (ex: the first spacer 141 and the second spacer 142) and the contact etch stop layer 16 are made of different materials. For example, the first spacer 141, the second spacer 142 and the contact etch stop layer 16 are oxide, nitride deposited by hollow cathode discharge (HCD), and nitride, respectively. Those materials are low etch resistance to the dry-etching or wet-etching removal of the dummy gate 12. In order to keep the final gate height HG of the structure, a higher dummy gate 12 is required to be constructed initially in this conventional process. In the 20 nm HKMG structure manufactured by the process of FIG. 1A˜FIG. 1D, if the required final gate height HG of the structure is 1000 Å, the heights of the polysilicon layer 121 and the hard mask layer 122 (FIG. 1A) should be about 1000 Å, respectively. However, the higher dummy gate in the HKMG process would have undesired effect on the electrical performance of the device; for example, having impact on the ability of lightly doped drain (LDD) implantation.